Semiconductor transistors, in particular field-effect controlled switching devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems. Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, low on-state resistance Ron and high breakdown voltages Ubd are often desired.
For this purpose charge compensation semiconductor devices were developed. The compensation principle is based on a mutual compensation of charges in n- and p-doped zones in the drift region of a MOSFET.
Typically, the charge compensation structure formed by p-type and n-type zones is for vertical charge compensation MOSFETs arranged below the actual MOSFET-structure with source regions, body regions and gate regions, and also below the associated MOS-channels which are arranged next to one another in the semiconductor volume of the semiconductor device or interleaved in one another in such a way that, in the off-state, their charges can be mutually depleted and that, in the activated state or on-state, there results an uninterrupted, low-impedance conduction path from a source electrode near the surface to a drain electrode arranged on the back side.
By virtue of the compensation of the p-type and n-type dopings, the doping of the current-carrying region can be significantly increased in the case of compensation components which results in a significant reduction of the on-state resistance Ron despite the loss of a current-carrying area. The reduction of the on-state resistance Ron of such semiconductor power devices is associated with a reduction of the heat loss, so that such semiconductor power devices with charge compensation structure remain “cool” compared with conventional semiconductor power devices.
Meanwhile, switching losses of semiconductor devices become more important. Depending on device operation, output charge QOSS and electric energy EOSS, respectively, stored in the space charge region formed in the off-state and during reverse bias, respectively, mainly determine the switching losses. The stored charge QOSS of semiconductor devices with charge compensation structures may be comparatively high. This may result in significant switching losses EOSS. In addition to enable reverse blocking, the output charge QOSS (at specific blocking voltage) has to be completely removed which results in switching delays.
Furthermore, to achieve both low on-state resistance Ron and high blocking voltage it is desirable that the dopings of the p-type and n-type zones of the charge compensation structure are well balanced. This typically poses high requirements for manufacturing and may limit down-scaling of the devices. For example, several processes of epitaxial growth and masked implantation followed by thermal drive-in may be used to form the charge compensation structure. During thermal drive-in, the implanted structures also grow in lateral direction. This limits the pitch between the p-type and n-type zones of the charge compensation structure.
Accordingly, there is a need to reduce switching losses and switching delays of semiconductor devices with charge compensation structures and to improve manufacturing of those devices.